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128mb: 8 meg x 16 mobile ddr sdram features pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 1 ?2004 micron technology, inc. all rights reserved. mobile ddr sdram mt46h8m16lf ? 2 meg x 16 x 4 banks for the latest data sheet, refer to micron?s web site: www.micron.com features ?v dd /v dd q = +1.8v 0.1v ? bidirectional data strobe per byte of data (dqs) ? internal, pipelined double data rate (ddr) architecture; two data accesses per clock cycle ? differential clock inputs (ck and ck#) ? commands entered on each positive ck edge ? dqs edge-aligned with data for reads; center- aligned with data for writes ? four internal banks for concurrent operation ? data masks (dm) for masking write data?one mask per byte ? programmable burst lengths: 2, 4, or 8 ? concurrent auto precharge option is supported ? auto refresh and self refresh modes ? 1.8v lvcmos-compatible inputs ? on-chip temperature sensor to control refresh rate ? partial array self refresh (pasr) ? selectable output drive (ds) ? clock stop capability options marking ?v dd /v dd q ? 1.8v/1.8v h ? configuration ? 8 meg x 16 (2 meg x 16 x 4 banks) 8m16 ?plastic package ? 60-ball vfbga (lead-free) 8mm x 10mm cf ? timing ? cycle time ? 7.5ns @ cl = 3 ? 10ns @ cl = 3 -75 -10 ? operating temperature range ? commercial (0 to +70c) ? industrial (-40c to +85c) none it figure 1: 60-ball vfbga assignment (top view) notes:1.d9 should be connected to v ss or v ss q in normal operations. table 1: configuration addressing architecture 8 meg x 16 configuration 2 meg x 16 x 4 refresh count 4k row addressing 4k (a0?a11) bank addressing 4 (ba0, ba1) column addressing 512k (a0?a8) table 2: key timing parameters speed grade clock rate access time cl = 2 cl = 3 cl = 2 cl = 3 -75 83 mhz 133 mhz 6.5ns 6.0ns -10 67 mhz 104 mhz 7.0ns 7.0ns 1 2 3 4 6 7 8 9 5 a b c d e f g h j k v ss q dq14 dq12 dq10 dq8 nc ck# nc a8 a5 v ss v dd q v ss q v dd q v ss q v ss cke a9 a6 v ss dq15 dq13 dq11 dq9 udqs udm ck a11 a7 a4 v dd q dq1 dq3 dq5 dq7 nc we# cs# a10 /ap a2 dq0 dq2 dq4 dq6 ldqs ldm cas# ba0 a0 a3 v dd v ss q v dd q test 1 v dd q v dd ras# ba1 a1 v dd
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 2 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram table of contents table of contents options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 fbga part marking decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 standard mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 deselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 no operation (nop). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 load mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 auto precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 burst terminate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 auto refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 self refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 bank/row activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 3 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram list of figures list of figures figure 1: 60-ball vfbga assignment (top view ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: functional block diagram (8 meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 figure 3: standard mode register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4: cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5: extended mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 6: clock stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 7: activating a specific row in a specific bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 8: example: meeting t rcd ( t rrd) min when 2 < t rcd ( t rrd) min/ t ck 3 . . . . . . . . . . . . . . . . . . . . . .20 figure 9: read command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 10: read burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 11: consecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 12: nonconsecutive read bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 13: random read accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 14: terminating a read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 15: read-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 16: read-to-precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 17: write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 18: write burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 19: consecutive write-to-write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 20: nonconsecutive write-to-write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 21: random write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 figure 22: write-to-read ? uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 figure 23: write-to-read ? interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 figure 24: write-to-read ? odd number of data, interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 25: write-to-precharge ? uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 26: write-to-precharge ? interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 27: write-to-precharge ? odd number of data, interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 28: precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 29: power-down command (active or precharge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 30: typical self-refresh current vs . temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 figure 31: x16 data output timing ? t dqsq, t qh, and data valid window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 figure 32: data output timing ? t ac and t dqsck. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 33: data input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 34: initialize and load mode regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 figure 35: power-down mode (active or prec harge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 figure 36: auto refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 figure 37: self refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 figure 38: bank read ? without auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 figure 39: bank read ? with auto precharg e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 figure 40: bank write ? without auto precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 figure 41: bank write ? with auto precharg e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 figure 42: write ? dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 figure 43: 60-ball vfbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 4 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram list of tables list of tables table 1: configuration addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 2: key timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table 3: 128mb mobile ddr sdram part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 4: 60-ball vfbga ball description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 5: burst definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 6: truth table ? commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 7: truth table ? dm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 8: truth table ? cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 table 9: truth table ? current state bank n - command to bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 10: truth table ? current state bank n - command to bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 11: absolute maximum dc ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 12: ac/dc electrical characteristics an d operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 table 13: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 14: i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 table 15: electrical characteristics and re commended ac operating conditions . . . . . . . . . . . . . . . . . . . . . . .50
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 5 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram fbga part marking decoder fbga part marking decoder due to space limitations, fbga-packaged components have an abbreviated part marking that is different from the part number. micron?s new fbga part marking decoder makes it easier to understand th is part marking. visit the web site at www.micron.com/decoder . general description the 128mb mobile ddr sdram is a high -speed cmos, dynamic random-access memory containing 134,271,728 bits. it is in ternally configured as a quad-bank dram. each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. the 128mb mobile ddr sdram uses a double da ta rate architecture to achieve high- speed operation. the double data rate architecture is essentially a 2 n -prefetch architec- ture with an interface designed to transfer two data words per clock cycle at the i/o balls. a single read or writ e access for the 128mb ddr sdra m effectively consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two corresponding n -bit wide, one-half-clock-cycle data transfers at the i/o balls. a bidirectional data strobe (dqs) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a st robe transmitted by the mobile ddr sdram during reads and by the memory controller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. the x16 offering has two data strobes, one for the lower byte and one for the upper byte. the 128mb mobile ddr sdram operates from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dq s, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the mobile ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coin- cident with the active command are used to select the bank and row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting co lumn location for the burst access. the mobile ddr sdram provides for programmable read or write burst lengths of 2, 4, or 8. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. as with standard sdr sdrams, the pipeline d, multibank architec ture of mobile ddr sdrams allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. table 3: 128mb mobile ddr sdram part numbers part number configuration i/o drive level temperature option MT46H8M16LFCF-75 8 meg x 16 programmable drive 0c to +70c MT46H8M16LFCF-75it 8 meg x 16 programmable drive -40c to +85c mt46h8m16lfcf-10 8 meg x 16 programmable drive 0c to +70c mt46h8m16lfcf-10it 8 meg x 16 programmable drive -40c to +85c
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 6 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram general description an auto-refresh mode is provided, along wi th a power saving power-down mode. self refresh mode offers temperature compensation through an on-chip temperature sensor and partial array self refresh, which allow us ers to achieve additional power saving. the temperature sensor is enabled by default and the partial array self refresh can be programmed through the extended mode register. notes: 1. throughout the data sheet, the various figures and text refer to dqs as ?dq.? the dq term is to be interpreted as any and all dq collectively, unless specifically stated oth- erwise. additionally, the x16 is divided into two bytes?the lower byte and upper byte. for the lower byte (dq0?dq7) dm refers to ldm and dqs refers to ldqs; and for the upper byte (dq8?dq15) dm refers to udm and dqs refers to udqs. 2. complete functionality is described th roughout the document and any page or dia- gram may have been simplified to convey a topic and may not be inclusive of all requirements. 3. any specific requirement takes precedence over a general statement. figure 2: functional block diagram (8 meg x 16) 12 ra s # c a s # row- addre ss mux c k cs # we# c k# c ontrol lo g i c c olumn- addre ss c ounter/ lat c h s tandard mode re g i s ter extended mode re g i s ter 9 c ommand de c ode a0?a11, ba0, ba1 c ke 12 addre ss re g i s ter 14 25 6 (x32) i/o g atin g dm ma s k lo g i c c olumn de c oder bank0 memory array (4,09 6 x 25 6 x 32) bank0 row- addre ss lat c h and de c oder 4,09 6 bank c ontrol lo g i c 14 bank1 bank2 bank3 12 8 2 2 refre s h c ounter 1 6 1 6 1 6 2 input re g i s ter s 2 2 2 2 r c vr s 2 32 32 4 32 c k out data dq s ma s k data c k c k in drvr s mux dq s g enerator 1 6 1 6 1 6 1 6 1 6 32 dq0? dq15 ldq s udq s 2 read lat c h write fifo & driver s 1 c ol0 c ol0 8,192 s en s e amplifier s ldm, udm c k
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 7 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram ball description ball description table 4: 60-ball vfbga ball description ball numbers symbol type description g2, g3 ck, ck# input clock: ck is the system clock input. ck and ck# are differen tial cloc k inputs. all address and control in put signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. input and output data is referenced to the crossing of ck and ck# (both directions of the crossing). g1 cke input clock enable: cke high activates and cke low deactivates the internal clock signals, inpu t buffers, and output drive rs. taking cke low allows precharge power-down and self refresh operations (all banks idle), or active power-down (row active in any bank). cke is synchronous for all functions expect self refresh exit. all input buffers (except cke) are disabled during power-dow n and self refresh modes. h7 cs# input chip select: cs# enables (registered lo w) and disables (registered high) the command decoder. all commands are ma sked when cs# is registered high. cs# provides for external bank selection on systems wi th multiple banks. cs# is considered part of the command code. g9, g8, g7 ras#, cas#, we# input command inputs: ras#, cas#, and we # (along with cs#) define the command being entered. f2, f8 udm, ldm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high alo ng with that input data during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, the dm loading is designed to match that of dq and dqs balls. for the x16, ldm is dm for dq0? dq7 and udm is dm for dq8?dq15. h8, h9 ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write, or precharge command is being applied. ba0 and ba1 also determine which mode register (standar d mode register or extended mode register) is loaded during a load mode register command. j8, j9, k7, k8, k2, k3, j1, j2, j3, j7, h1, h2 a0?a11 input address inputs: provide the row addr ess for active commands, and the column address and auto precharge bi t (a10) for read or write commands, to select one location out of the me mory array in the respective bank. during a precharge command, a10 determines whether the precharge applies to one bank (a10 low, bank sele cted by ba0, ba1) or all banks (a10 high). the address inputs also provid e the op-code during a load mode register command. a8, b7, b8, c7, c8, d7, d8, e7 e3, d2, d3, c2, c3, b2, b3, a2 dq0?dq15 i/o data input/output: data bus for x16. e2, e7 udqs, ldqs i/o data strobe: output with read data, input with write data. dqs is edge- aligned with read data, centered in wr ite data. it is used to capture data. a7, b1, c9, d1, e9 v dd q supply dq power supply. a3, b9, c1, e1 v ss q supply dq ground: isolated on the die for improved noise immunity. a9, f9, k9 v dd supply power supply. a1, f1, k1 v ss supply ground. f3, f7, h3 nc input no connect. these pins should be left unconnected. d9 test input test pin: must be tied to v ss or v ss q in normal operations.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 8 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram functional description functional description the 128mb mobile ddr sdram is a high -speed cmos, dynamic random-access memory containing 134,271,728-bits. it is in ternally configured as a quad-bank dram. each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits. the 128mb mobile ddr sdram uses a double da ta rate architecture to achieve high- speed operation. the double data rate architecture is essentially a 2 n -prefetch architec- ture, with an interface designed to transfer two data words per clock cycle at the i/o balls. single read or write access for the 128mb mobile ddr sdram consists of a single 2 n -bit wide, one-clock-cycle data transfer at the internal dram core and two corre- sponding n -bit wide, one-half-clock-cycle data transfers at the i/o balls. read and write accesses to the mobile ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coin- cident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank; a0?a11 select the ro w). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. it should be noted that the dll that is ty pically used on standard ddr devices is not necessary on the mobile ddr sdram. it has been omitted to save power. prior to normal operation, the mobile ddr sdram must be initialized. the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. initialization mobile ddr sdrams must be powered up and initialized in a predefined manner. oper- ational procedures other than those specif ied may result in undefined operation. if there is an interruption to the device power, the initialization routine should be followed to ensure proper functionality of the mobile ddr sdram. to properly initialize the mobile ddr sdram, the following sequence must be followed: 1. it is recommended the core power (v dd ) and i/o power (v dd q) be from the same power source and brought up simultaneously. if separate power sources are used, v dd must lead v dd q. 2. once power supply voltages are stable and the cke has been driven high, it is safe to apply the clock. 3. once the clock is stable, a 200s minimum delay is required by the mobile ddr sdram prior to applying an executable co mmand. during this time, nop or dese- lect commands must be issued on the command bus. 4. issue a precharge all command. 5. issue nop or deselect commands for at least t rp time. 6. issue an auto refresh command followed by nop or deselect commands for at least t rfc time. issue a second auto refresh command followed by nop or dese- lect commands for at least t rfc time. as part of the individualization sequence, two auto refresh commands must be issued. typically, both of these commands are issued at this stage as de scribed above. alternately, the second auto-refresh com- mand and nop or deselect sequence can be issued after step 10.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 9 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram register definition 7. using the load mode register command, load the standard mode register as desired. 8. issue nop or deselect commands for at least t mrd time. 9. using the load mode register command, load the extended mode register to the desired operating modes. note that the sequ ence in which the standard and extended mode registers are programmed is not critical. 10. issue nop or deselect commands for at least t mrd time. the mobile ddr sdram has been properly initialized and is ready to receive any valid command. register definition mode registers the mode registers are used to define the sp ecific mode of operation of the mobile ddr sdram. there are two mode registers used to specify the operational characteristics of the device. the standard mode register, which exists for all sdram devices, and the extended mode register, which is exists on all mobile sdram devices. standard mode register the standard mode register definition includ es the selection of a burst length, a burst type, a cas latency and an operating mode, as shown in figure 3 on page 10. the stan- dard mode register is programmed via the load mode register command (with ba0 = 0 and ba1 = 0) and will retain the stored information until it is programmed again. reprogramming the standard mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded when all banks are idle and no bursts are in progress, and the co ntroller must wait the specified time before initiating the subsequent operat ion. violating either of these requirements will result in unspecified operation. mode register bits a0?a2 specify the burst le ngth, a3 specifies the type of burst (sequen- tial or interleaved), a4?a6 specify the cas latency, and a7?a11 specify the operating mode. note: standard refers to meeting jedec-standard mode register definitions. burst length read and write accesses to the mobile ddr sdram are burst oriented, with the burst length being programmable, as shown in fi gure 3 on page 10. the burst length deter- mines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 are available for both the sequential and the interleaved burst types. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses fo r that burst take place within this block, meaning that the burst will wrap until a bo undary is reached. the block is uniquely selected by a1?a i when bl = 2, by a2?a i when bl = 4, by a3?a i when bl = 8 (where a i is
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 10 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram register definition the most significant column address bit for a given configuration). the remaining (least significant) address bit(s) is (are) used to se lect the starting location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address. see table 5 on page 11 for more information. read latency the read latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output data. the latency can be set to 2 or 3 clocks, as shown in figure 3 on page 10. for cl = 3, if the read command is registered at clock edge n , then the data will nomi- nally be available at ( n + 2 clocks + t ac ) . for cl = 2, if the read command is registered at clock edge n , then the data will be nominally be available at ( n + 1 clock + t ac ). reserved states should not be used as unknown operation or incompatibility with future versions may result. figure 3: standard mode register definition s houl d b e pro g ramme d to ?0? to ensure c ompati b ility with future d evi c es. m3 = 0 reserve d 2 4 8 reserve d reserve d reserve d reserve d m3 = 1 reserve d 2 4 8 reserve d reserve d reserve d reserve d 0 1 burst type s equential interleave d c a s laten c y reserve d reserve d 2 3 reserve d reserve d reserve d reserve d burst len g th m0 0 1 0 1 0 1 0 1 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m 6 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 mo d e re g ister a dd ress bus 97 6 54 3 821 burst len g th c a s laten c ybt operatin g mo d e 0 a11 m11 a10 m10 a9 m9 a8 m8 a7 m7 a 6 m 6 a5 m5 a4 m4 a3 m3 a2 m2 a1 m1 a0 m0 10 11 12 ba0 m12 ba1 m13 0 13 0 m11 0 ? m10 0 ? m9 0 ? m8 0 ? m7 0 ? operatin g mo d e vali d ? normal operation all other states reserve d mo d e re g ister definintion base mo d e re g ister reserve d exten d e d mo d e re g ister resereve d m13 m12
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 11 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram register definition figure 4: cas latency notes: 1. bl = 4 in the cases shown. 2. shown with nominal t ac and nominal t dsdq. table 5: burst definition burst length starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4a1a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 c k c k# c k c k# t0 t1 t2 t2n t3 t3n t1n c ommand dq dq s c l = 2 t0 t1 t2 t2n t3 t3n don ? t c are tran s itionin g data read nop nop nop c ommand dq dq s c l = 3 read nop nop nop d out n d out n + 1 d out n + 3 d out n + 2 d out n d out n + 1 1 c lo c k a c t 2 c lo c k a c t
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 12 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram register definition operating mode the normal operating mode is selected by issuing a load mode register set command with bits a7?a11 each set to zero , and bits a0?a6 set to the desired values. all other combinations of values for a7?a11 are reserved for future use and/or test modes. test modes and reserved states shou ld not be used because unknown operation or incompatibility with future versions may result. extended mode register the extended mode register controls functi ons specific to low power operation. these additional functions include drive strength, temperature compensated self refresh, and partial array self refresh. temperature compensated self refresh on this version of the mobile ddr sdram, a temperature sensor is implemented for automatic control of the self refresh osci llator on the device. programming of the temperature compensated self refresh (tcsr) bits will have no effect on the device. the self refresh oscillator will continue refresh at the factory programmed optimal rate for the device temperature. partial array self refresh for further power savings during self refres h, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh. the refresh options are as follows: ? full array: banks 0, 1, 2, and 3 ? half array: banks 0 and 1 ?quarter array: bank 0 write and read commands can still occur du ring standard operation, but only the selected banks will be refreshed during self refresh. data in banks that are disabled will be lost. output driver strength because the mobile ddr sdram is designed fo r use in smaller systems that are mostly point to point, an option to control the drive strength of the output buffers is available. drive strength should be selected based on th e expected loading of the memory bus. bits a5 and a6 of the extended mode register can be used to select the driver strength of the dq outputs. there are three allowable settings for the output drivers (25 ohm internal impedance, 55 ohm internal impedance, and 80 ohm internal impedance).
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 13 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram register definition figure 5: extended mode register notes: 1. on-chip temperature sensor is used in place of tcsr. setting these bits will have no effect. stopping the external clock one method of controlling the power efficiency in applications is to throttle the clock which controls the sdram. there are two basic ways to control the clock: 1. change the clock frequency. 2. stop the clock. both of these are specific to the applicatio n and its requirements and both allow power savings due to possible less transitions on the clock path. the mobile ddr sdram allows the clock to ch ange frequency during operation, only if all the timing parameters are met with resp ect to that change and all refresh require- ments are satisfied. the clock can also be stopped if there are no data accesses in progress, either writes or reads that would be affected by this change. if a write or a read is in progress the entire data burst must be comple te prior to stopping the clock. for reads, a burst completion is defined when the read postamble is satisfied; for writes, a burst completion is defined when the write postamble and t wr or t wtr are satisfied. cke must be held high with ck = low and ck# = high for the full duration of the clock stop mode. one clock cycle and at least one nop is required after the clock is restarted before a valid command can be issued. figure 6 on page 14 illustrates the clock stop mode. exten d e d mo d e re g ister a dd ress bus 9 7 6 5 4 3 8 2 1 pa s r t cs r 1 d s set to ?0? 0 a11 e11 a10 e10 a9 e9 a8 e8 a7 e7 a 6 e 6 a5 e5 a4 e4 a3 e3 a2 e2 a1 e1 a0 e0 10 11 12 e2 0 0 0 0 1 1 1 1 e1 0 0 1 1 0 0 1 1 e0 0 1 0 1 0 1 0 1 partial array s elf refresh c overa g e full array (all banks) half array (ba1 = 0) quarter array (ba1 = ba0 = 0) reserve d reserve d reserve d reserve d reserve d e 6 0 0 1 1 e5 0 1 0 1 driver s tren g th full s tren g th driver half s tren g th driver quarter s tren g th driver reserve d ba0 e12 ba1 e13 1 13 0 0 1 1 mo d e re g ister definintion base mo d e re g ister reserve d exten d e d mo d e re g ister reserve d e13 0 1 0 1 e12 0 e11 0 ? e10 0 ? e9 0 ? e8 0 ? e7 0 ? vali d ? normal operation operatin g mo d e all other states reserve d e 6 ?e0
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 14 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram register definition figure 6: clock stop mode notes: 1. prior to ta1, the device is in cloc k stop mode. to exit, at least one nop is re q uired before any valid command. 2. any valid command is allowed, device is not in clock suspend mode. 3. any dram operation already in process must be completed before entering clock stop mode. this includes t rcd, t rp, t rfc, t mrd, t wr, all data-out for read bursts. 4. to enter and maintain a clock stop mo de: ck = low, ck# = high, cke = high. exit c lo c k stop mo d e c ke c k c k# c ommand ( ) ( ) ( ) ( ) nop nop ta1 ta2 t b 3t b 4 don ? t c are a dd ress dq, dq s hi g h-z ( ) ( ) ( ) ( ) ( ) ( ) enter c lo c k stop mo d e 4 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) all dram a c tivities must b e c omplete 3 c md 2 vali d c md 2 vali d nop 1 ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 15 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram commands commands table 6 and table 7 provide quick references of available commands. this is followed by a written description of each command. th ree additional truth tables (table 8 on page 42, table 9 on page 43, and table 10 on page 45) provide cke commands and current/next state information. notes: 1. cke is high for all comma nds shown except self refresh. 2. ba0?ba1 select either the standard mode register or the exte nded mode register (ba0 = 0, ba1 = 0 select the standard mode re gister; ba0 = 1, ba1 = 0 select extended mode register; other combinations of ba0?ba1 are reserved). a0?a11 provide the op-code to be written to the selected mode register. 3. ba0?ba1 provide bank address and a0?a11 provide row address. 4. ba0?ba1 provide bank address; a0?a8 provide column address; a10 hi gh enables the auto precharge feature (nonpersistent), and a10 low disables the auto precharge feature. 5. a10 low: ba0?ba1 determine which bank is precharged. a10 high: all banks are precharged and ba0?ba1 are ? don?t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls ro w addressing; all inputs and i/os are ? don?t care ? except for cke. 8. applies only to read bursts wi th auto precharge disabled; this command is undefined (and should not be used) for read bursts with au to precharge enabled and for write bursts. 9. deselect and nop are functionally interchangeable. note: used to mask write data; provided coincident with corresponding data. table 6: truth table ? commands note 1 applies to all co mmands; all states and se q uences not shown are reserved and/or illegal. name (function) cs# ras# cas# we# addr notes deselect (nop) hxxx x 9 no operation (nop) l hhh x 9 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) lhlhbank/col4 write (select bank and colu mn, and start write burst) l h l l bank/col 4 burst terminate lhhl x 8 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh (refresh all or single bank) or self refresh (enter self refresh mode) lllhx6, 7 load mode register (standard or extended mode registers) llllop-code2 table 7: truth table ? dm operation name (function) dm dq write enable l valid write inhibit hx
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 16 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram commands deselect the deselect function (cs# high) prevents new commands from being executed by the mobile ddr sdram. the mobile ddr sdram is effectively deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected ddr sdram to perform a nop (cs# = low, ras# = cas# = we# = high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. load mode register the mode registers are loaded via inputs a0?a11. see mode register descriptions in ?register definition? on page 9. the load mode register command can only be issued when all banks are idle, and a subseq uent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0?a i (where i = 8 for x16) selects the starting column location. the value on input a10 deter- mines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subseq uent accesses. input data appearing on the dqs is written to the memory array subject to the dm input logic level appearing coinci- dent with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specified time ( t rp) after the precharge command is issued. except in the case of
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 17 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram commands concurrent auto precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. inpu t a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank . a precharge command will be treated as a nop if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual-bank precharge func- tion described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon co mpletion of the read or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each indi- vidual read or write command. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is in itiated at the earliest valid stage within a burst. this ?earliest valid stage? is determ ined as if an explicit precharge command was issued at the earliest possible time, without violating t ras (min), as described for each burst type in ?operations? on page 19. the user must not issue another command to the same bank until the precharge time ( t rp) is completed. burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated, as shown in ?operations? on page 19. the open page which the read burst was terminated from remains open. auto refresh auto refresh is used during normal op eration of the mobile ddr sdram and is analogous to cas#-befor e-ras# (cbr) refresh in fpm/edo drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a ?don?t care? during an auto refresh command. the 128mb mobile ddr sdram requires auto refresh cycles at an average interval of 15.625s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexi- bility in the absolute refr esh interval is provided. although not a jedec requirement, to provide for future functionality features, cke must be active (high) during the auto refresh period. the auto refresh period begins when the auto refresh command is registered and ends t rfc later.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 18 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram commands self refresh the self refresh command can be used to retain data in the mobile ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the mobile ddr sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low ). all command and address input signals except cke are ?don?t care? during self refresh. during self refresh, the device is refreshed as identified in the external mode register (see pasr setting). the procedure for exiting self refresh requires a sequence of commands. first, ck must be stable prior to cke going back high. once cke is high, the mobile ddr sdram must have nop commands issued for t xsr is required for the completion of any internal refresh in progress.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 19 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations operations bank/row activation before any read or write commands can be issued to a bank within the mobile ddr sdram, a row in that bank must be ?opene d.? this is accomplished via the active command, which selects both the bank and the row to be activated, as shown in figure 7. after a row is opened with an active command, a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write command can be entered. for example, a t rcd specification of 20ns with a 133 mhz clock (7.5ns period) results in 2.7 clocks rounded to 3. this is reflected in figure 8 on page 20,which covers any case where 2 < t rcd (min)/ t ck 3. (figure 8 also shows the same case for t rcd; the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been ?closed? (precharged). the minimum time interval between successive active comma nds to the same bank is defined by t rc. a subsequent active command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. the minimum time interval between successive active co mmands to different banks is defined by t rrd. figure 7: activating a specific row in a specific bank cs # we# c a s # ra s # c ke a0?a11 ra ra = row a dd ress ba = bank a dd ress hi g h ba0, ba1 ba c k c k# don ? t c are
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 20 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 8: example: meeting t rcd ( t rrd) min when 2 < t rcd ( t rrd) min/ t ck 3 reads read bursts are initiated with a read command, as shown in figure 9 on page 21. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the read commands used in the following illustrations, auto precharge is disabled. during read bursts, the valid data-out elem ent from the starting column address will be available following the cas latency after the read command. each subsequent data- out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of ck and ck#). figure 10 on page 22 shows general timing for each possible cas latency setting. dqs is driven by the mobile ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data-out el ement is known as the read postamble. upon completion of a burst, assuming no other commands have been initiated, the dqs will go high-z. a detailed explanation of t dqsq (valid data-out skew), t qh (data-out window hold), the valid data window are depicted in figure 31 on page 55. a detailed explanation of t dqsck (dqs transition skew to ck) and t ac (data-out transition skew to ck) is depicted in figure 32 on page 56. data from any read burst may be concatenat ed with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be main- tained. the first data element from the new burst follows either the last element of a completed burst or the last desired data elem ent of a longer burst which is being trun- cated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). this is shown in figure 11 on page 23. a read command can be initiated on any clock cycle following a previous read command. nonconsecutive read data is sh own for illustration in figure 12 on page 24. full-speed random read accesses within a page (or pages) can be performed, as shown in figure 13 on page 25. t c ommand ba0, ba1 a c ta c t nop rrd t r c d c k c k# bank x bank y a0-a11 row row nop rd/wr nop bank y c ol nop t0 t1 t2 t3 t4 t5 t 6 t7 don ? t c are nop
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 21 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 9: read command cs # we# c a s # ra s # c ke c a a0?a9 a10 ba0,1 hi g h en ap di s ap ba a11 c k c k# c a = c olumn a dd ress ba = bank a dd ress en ap = ena b le auto pre c har g e di s ap = disa b le auto pre c har g e don ? t c are
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 22 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 10: read burst notes: 1. d out n = data-out from column n . 2. bl = 4. 3. shown with nominal t ac, t dqsck, and t dqsq. c k c k# c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t0 t1 t2 t3 t2n t3n t4 t5 t1n d out n d out n + 1 d out n + 3 d out n + 2 c ommand read nop nop nop nop nop addre ss bank a, c ol n don ? t c are tran s itionin g data dq dq s c l = 2 d out n d out n + 1 d out n + 3 d out n + 2 c ommand read nop nop nop nop nop addre ss bank a, c ol n dq dq s c l = 3
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 23 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 11: consecutive read bursts notes: 1. d out n (or b ) = data-out from column n (or column b ). 2. bl = 4 in the cases shown (app lies for bursts of 8 as well; if bl = 2, the bst command shown can be a nop). 3. shown with nominal t ac, t dqsck, and t dqsq. 4. this example represents consecutive read commands issued to the device. c k c k# c k c k# t0 t1 t2 t3 t2n t3n t4 t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t5 t4n t5n c ommand read nop read nop nop nop addre ss bank, c ol n bank, c ol b c ommand read nop read nop nop nop addre ss bank, c ol n bank, c ol b c ommand addre ss don ? t c are tran s itionin g data dq dq s c l = 2 d out n d out n + 1 d out n + 3 d out n + 2 d out b d out b + 2 d out b + 1 d out b + 3 dq dq s c l = 3 d out n d out n + 1 d out n + 3 d out n + 2 d out b d out b + 1
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 24 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 12: nonconsecutive read bursts notes: 1. d out n (or b ) = data-out from column n (or column b ). 2. bl = 4 in the cases shown (app lies for bursts of 8 as well; if bl = 2, the bst command shown can be a nop). 3. shown with nominal t ac, t dqsck, and t dqsq. 4. this example represents no nconsecutive read commands issued to the device. c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t 6 c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n t 6 c ommand read nop nop nop nop nop addre ss bank, c ol n read bank, c ol b don ? t c are tran s itionin g data dq dq s c l = 2 d out b d out b + 1 d out b + 2 c l = 2 c ommand read nop nop nop nop nop addre ss bank, c ol n read bank, c ol b dq dq s c l = 3 d out b c l = 3 d out n d out n + 1 d out n + 3 d out n + 2 d out n d out n + 1 d out n + 3 d out n + 2
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 25 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 13: random read accesses notes: 1. d out n (or x , b, g ) = data-out from column n ( or column x , column b , column g ). 2. bl = 4 in the cases shown (app lies for bursts of 8 as well; if bl = 2, the bst command shown can be a nop). 3. reads are to an active row in any bank. 4. shown with nominal t ac, t dqsck, and t dqsq. truncated reads data from any read burst may be truncated with a burst terminate command, as shown in figure 14 on page 26. the burst term inate latency is equal to the read (cas) latency, i.e., the burst terminate command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). data from any read burst must be complete d or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in figure 15 on page 27. the t dqss (min) case is shown; the t dqss (max) case has a longer bus idle time. ( t dqss [min] and t dqss [max] are defined in the section on writes.) a read burst may be followed by, or tr uncated with, a precharge command to the same bank provided that auto precharge was not activated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pairs are required by the n -prefetch architecture). this is shown in figure 16 on page 28. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note: part of the row precharge time is hidden during the access of the last data elements. c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n c k c k# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n c ommand read read read nop nop addre ss bank, c ol n bank, c ol x bank, c ol b bank, c ol x bank, c ol b read bank, c ol g c ommand addre ss c ommand addre ss read read read nop nop bank, c ol n read bank, c ol g don ? t c are tran s itionin g data dq dq s c l = 2 d out n d out n + 1 d out x + 1 d out x d out b d out g d out b + 1 d out g + 1 dq dq s c l = 3 d out n d out n + 1 d out x + 1 d out x d out b d out b + 1
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 26 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 14: terminating a read burst notes: 1. d out n = data-out from column n . 2. only valid for bl = 4 and bl = 8. 3. shown with nominal t ac, t dqsck, and t dqsq. 4. bst = burst terminate comm and; page remains open. 5. cke = high. c k c k# t0 t1 t2 t3 t2n t4 t5 t1n c ommand read b s t 4 nop nop nop nop addre ss bank a , c ol n don ? t c are tran s itionin g data dq dq s c l = 2 d out n d out n + 1 c k c k# t0 t1 t2 t3 t2n t4 t5 t3n c ommand read b s t 4 nop nop nop nop addre ss bank a , c ol n dq dq s c l = 3 d out n d out n + 1
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 27 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 15: read-to-write notes: 1. d out n = data-out from column n . 2. d in b = data-in from column b . 3. bl = 4 in the cases shown (app lies for bursts of 8 as well; if bl = 2, the bst command shown can be a nop). 4. shown with nominal t ac, t dqsck, and t dqsq. 5. bst = burst terminate comm and; page remains open. 6. cke = high. ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n t4n t5n ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t4n t5n ck don?t care transitioning data command read bst 5 nop nop nop address bank, col n write bank, col b dm t (nom) dqss dq dqs cl = 2 d out n d out n+1 d in b+1 d in d in d in b b+2 b+3 command read bst 5 nop nop address bank, col n write bank, col b dm t (nom) dqss dq dqs cl = 3 n n+1 b+1 b nop d out d out d in d in
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 28 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 16: read-to-precharge notes: 1. d out n = data-out from column n . 2. bl = 4 or an interrupted burst of 8. 3. shown with nominal t ac, t dqsck, and t dqsq. 4. read-to-precharge e q uals 2 clocks, which allows 2 data pairs of data-out. 5. a read command with auto pr echarge enabled, provided t ras (min) is met, would cause a precharge to be performed at x number of clock cycles after the read command, where x = bl / 2. 6. pre = precharge command; act = active command. ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n ck ck# t0 t1 t2 t3 t2n t3n t4 t5 t1n command 5 read nop pre nop nop act address bank a , col n bank a , ( a or all ) bank a , row dq dqs cl = 2 t rp t rp read nop pre nop nop act bank a , col n command 5 address bank a , ( a or all ) bank a , row dq dqs cl = 3 don?t care transitioning data d out n d out n + 1 d out n + 3 d out n + 2 d out n d out n + 1 d out n + 3 d out n + 2
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 29 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations writes write bursts are initiated with a write command, as shown in figure 17 on page 30. the starting column and bank addresses ar e provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at th e completion of the burst. for the write commands used in the following illustrations, auto precharge is disabled. during write bursts, the first valid data-in element will be registered on the first rising edge of dqs following the write command, and subsequent data elements will be registered on successive edges of dqs. the low state on dqs between the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and th e first corresponding rising edge of dqs ( t dqss) is specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle). all of the write diagrams show the nominal case, and where the two extreme cases (i.e., t dqss [min] and t dqss [max]) might not be intuitive, they have also been included. figure 18 on page 31 shows the nominal case and the extremes of t dqss for a burst of 4. upon completion of a burs t, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored. data for any write burst may be concatenat ed with or truncated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the previous write command. the first data elem ent from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2 n -prefetch architecture). figure 19 on page 32 shows concatenated burs ts of 4. an example of nonconsecutive writes is shown in figure 20 on page 32. full-speed random write accesses within a page or pages can be performed, as shown in figure 21 on page 33. data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, t wtr should be met, as shown in figure 22 on page 34. data for any write burst may be truncated by a subsequent read command, as shown in figure 23 on page 35. note that only the data-in pairs that are registered prior to the t wtr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figure 24 on page 36. data for any write burst may be followed by a subsequent precharge command. to follow a write without truncating the write burst, t wr should be met, as shown in figure 25 on page 37. data for any write burst may be truncated by a subsequent precharge command, as shown in figure 26 on page 38 and figure 27 on page 39. note that only the data-in pairs that are registered prior to the t wr period are written to the internal array, and any subsequent data-in should be masked with dm, as shown in figure 26 on page 38 and figure 27 on page 39. after the precharge command, a subsequent command to the same bank cannot be issued until t rp is met.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 30 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 17: write command note: dis ap = disa ble auto precharge en ap = enable auto precharge ba = bank address ca = column address cs # we# c a s # ra s # c ke c a a10 ba0,1 hi g h en ap di s ap ba c k c k# don ? t c are a0?a8 a11
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 31 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 18: write burst notes: 1. d in b = data-in for column b . 2. an uninterrupted burst of 4 is shown. 3. a10 is low with the write comm and (auto precharge is disabled). dq s t dqss (max) t dqss (nom) t dqss (min) t dq ss dm dq c k c k# c ommand write nop nop addre ss bank a , c ol b nop t0 t1 t2 t3 t2n dq s t dq ss dm dq dq s t dq ss dm dq d in b don ? t c are tran s itionin g data d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 32 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 19: consecutive write-to-write notes: 1. d in b ( n ) = data-in for column b ( n ). 2. an uninterrupted burst of 4 is shown. 3. each write command may be to any bank. figure 20: nonconsecutive write-to-write notes: 1. d in b ( n ) = data-in for column b ( n ). 2. an uninterrupted burst of 4 is shown. 3. each write command may be to any bank. c k c k# c ommand write nop write nop nop addre ss bank, c ol b nop bank, c ol n t0 t1 t2 t3 t2n t4 t5 t4n t3n t1n dq dq s dm don ? t c are tran s itionin g data t dq ss t dqss (nom) d in n d in n+1 d in n+2 d in n+3 d in b d in b+1 d in b+2 d in b+3 c k c k# c ommand write nop nop nop nop addre ss bank, c ol b write bank, c ol n t0 t1 t2 t3 t2n t4 t5 t4n t1n t5n dq dq s dm t dqss (nom) t dq ss don ? t c are tran s itionin g data d in b d in b + 1 d in b + 2 d in b + 3 d in n d in n + 1 d in n + 2 d in n + 3
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 33 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 21: random write cycles notes: 1. d in b ( or x , n , a , g ) = data-in for column b (or x, n, q, g ) 2. b' (or x, n, a, g ) = the next data-in following d in b ( x, n, a, g ), according to the programmed burst order. 3. programmed bl = 2, 4, or 8 in cases shown. 4. each write command may be to any bank. t dq ss (nom) c k c k# c ommand write write write write nop addre ss bank, c ol b bank, c ol x bank, c ol n bank, c ol g write bank, c ol a t0 t1 t2 t3 t2n t4 t5 t4n t1n t3n t5n dq dq s dm din b d in b' d in x d in x' d in n d in n' d in a d in a' d in g d in g ' don ? t c are tran s itionin g data
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 34 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 22: write-to-read ? uninterrupting notes: 1. d in b = data-in for column b ; d out n = data-out for column n . 2. an uninterrupted burst of 4 is shown. 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. the read and write commands are to same device. however, the read and write com- mands may be to different devices, in which case t wtr is not re q uired and the read com- mand could be applied earlier. 5. a10 is low with the write comm and (auto precharge is disabled). t dqss (nom) c k c k# c ommand write nop nop read nop nop addre ss bank a , c ol b bank a , c ol n nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 t 6 n t wtr c l = 2 dq dq s dm d out n t dqss (min) c l = 2 dq dq s dm t dqss (max) c l = 2 dq dq s dm t dq ss t dq ss t dq ss don ? t c are tran s itionin g data d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d out n+1 d out n d out n+1 d out n d out n+1 t5n
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 35 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 23: write-to-read ? interrupting notes: 1. d in b = data-in for column b ; d out n = data-out for column n . 2. an interrupted burst of 4 is show n; two data elements are written. 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. dqs is re q uired at t2 and t2n (nominal case) to register dm. 6. if the burst of 8 was used, dm and dqs would be re q uired at t3 and t3n because the read command would not mask th ese two data elements. t dqss (nom) c k c k# c ommand write nop nop nop nop nop addre ss bank a , c ol b bank a , c ol n read t0 t1 t2 t3 t2n t4 t5 t5n t1n t 6 t 6 n t wtr c l = 3 dq dq s dm d in b d out n t dqss (min) c l = 3 dq dq s dm t dqss (max) c l = 3 dq dq s dm don ? t c are tran s itionin g data t dq ss t dq ss t dq ss d in b+1 d in b+1 d in b d in b+1 d in b d out n+1 d out n d out n+1 d out n d out n+1
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 36 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 24: write-to-read ? odd number of data, interrupting notes: 1. d in b = data-in for column b ; d out n = data-out for column n . 2. an interrupted burst of 4 is shown; one data element is written, three are masked. 3. t wtr is referenced from the first positive ck edge after the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. dqs is re q uired at t2 and t2n (nominal case) to register dm. 6. if the burst of 8 was used, dm and dqs would be re q uired at t3 and t3n because the read command would not mask th ese two data elements. t dqss (nom) c k c k# c ommand write nop nop nop nop nop addre ss bank a , c ol b bank a , c ol n read t0 t1 t2 t3 t2n t4 t5 t5n t1n t 6 t 6 n t wtr c l = 3 dq dq s dm d in b d out n t dqss (min) c l = 3 dq dq s dm t dqss (max) c l = 3 dq dq s dm don ? t c are tran s itionin g data t dq ss t dq ss t dq ss d in b d in b d out n + 1 d out n d out n + 1 d out n d out n + 1
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 37 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 25: write-to-precharge ? uninterrupting notes: 1. d in b = data-in for column b . 2. an uninterrupted burst of 4 is shown. 3. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 4. the precharge and write commands are to same device. however, the precharge and write commands may be to differ ent devices, in which case t wr is not re q uired and the precharge command coul d be applied earlier. 5. a10 is low with the write comm and (auto precharge is disabled). 6. pre = precharge command. t dqss (nom) c k c k# c ommand write nop nop nop nop addre ss bank a , c ol b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 dq dq s dm t dq ss t dqss (min) dq dq s dm t dq ss t dqss (max) dq dq s dm t dq ss don ? t c are tran s itionin g data d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 d in b d in b+1 d in b+2 d in b+3 t wr pre 6
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 38 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 26: write-to-precharge ? interrupting notes: 1. d in b = data-in for column b . 2. an interrupted burst of 8 is shown. 3. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. pre = precharge command. 6. dqs is re q uired at t4 and t4n (nominal case) to register dm. 7. if a burst of 4 was used, dqs and dm would not be re q uired at t3, t3n, t4, and t4n. t dqss (nom) c k c k# c ommand write nop nop nop nop addre ss bank a , c ol b bank (a or all) nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 dq dq s dm t dq ss t dqss (min) dq dq s dm t dq ss t dqss (max) dq dq s dm t dq ss don ? t c are tran s itionin g data d in b d in b+1 d in b d in b+1 d in b d in b+1 t wr pre 5 t4n t3n
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 39 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations figure 27: write-to-precharge ? odd number of data, interrupting notes: 1. d in b = data-in for column b . 2. an interrupted burst of 8 is shown. 3. t wr is referenced from th e first positive ck edge af ter the last data-in pair. 4. a10 is low with the write comm and (auto precharge is disabled). 5. pre = precharge command. 6. dqs is re q uired at t4 and t4n (nominal case) to register dm. 7. if a burst of 4 was used, dqs and dm would not be re q uired at t3, t3n, t4, and t4n. t dq ss t dqss (nom) c k c k# c ommand write nop nop pre 7 nop nop addre ss bank a , c ol b bank, ( a or all ) nop t0 t1 t2 t3 t2n t4 t5 t1n t 6 t wr t rp dq dq s dm di b t dq ss t dqss (min) dq dq s dm t dq ss t dqss (max) dq dq s dm di b di b don ? t c are tran s itionin g data t3n t4n
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 40 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations precharge the precharge command (figure 28) is used to deactivate the open row in a partic- ular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when all banks are to be precharged, inputs ba0, ba1 are treated as ?don?t care.? once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. figure 28: precharge command notes: 1. ba = bank address. all = all banks to be precharged, ba1, ba0 are ? don't care. ? single = only bank selected by ba1 and ba0 will be precharged. cs # we# c a s # ra s # c ke a10 ba0,1 hi g h all s in g le ba c k c k# don ? t c are a0-a9, a11
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 41 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram operations power-down power-down is entered when cke is registered low. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down deactivates the input an d output buffers, including ck and ck#. exiting power-down requires the device to be at the same voltage as when it entered power-down and a stable clock. note: the power-down duration is limited by the refresh requirements of the device. while in power-down, cke low must be maintained at the inputs of the mobile ddr sdram, while all other input si gnals are ?don?t care.? the power-down state is exited when cke is registered high (in conjun ction with a nop or deselect command). nops or deselect commands must be ma intained on the command bus until t xp is satisfied. figure 29: power-down command (active or precharge) cs # ra s #, c a s #, we# c ke ba0,1 c k c k# don ? t c are a0?a11 ra s #, c a s #, we# cs # ba0?ba1 or
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 42 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram truth tables truth tables notes: 1. cke n is the logic state of cke at clock edge n ; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n . 3. command n is the command regi stered at clock edge n , and action n is a result of command n . 4. all states and se q uences not shown are illegal or reserved. 5. t cke pertains. 6. deselect or nop commands should be issued on any clock edges occurring during the t xp period. 7. the clock must toggle at least once during the t xp period. 8. deselect or nop commands should be issued on any clock edges occurring du ring the t xsr period. 9. the clock must toggle at least once during the t xsr period. table 8: truth table ? cke notes: 1?5 cke n-1 cke n current state command n action n notes l l (active) power-down x maintain (active) power-down l l (precharge) power-down x mai ntain (precharge) power-down l l self refresh x maintain self refresh l h (active) power-down deselect or nop exit (active) power-down 6, 7 l h (precharge) power-down de select or nop exit (pre charge) power-down 6, 7 l h self refresh deselect or nop exit self refresh 8, 9 h l bank(s) active dese lect or nop (active ) power-down entry h l all banks idle deselect or no p (precharge) power-down entry h l all banks idle auto refresh self refresh entry h h see table 10 on page 45 h h see table 10 on page 45
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 43 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram truth tables notes: 1. this table applies when cke n-1 was high and cke n is high and after t xsr has been met (if the previous state was self refresh) and after t xp has been met (if the previous state was power-down). 2. this table is bank-specific, except where note d (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). exceptions are covered in the notes below. 3. current state definitions: 4. the following states must not be interrupted by a command issued to the same bank. com- mand inhibit or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during th ese states. allowable commands to the other bank are determined by its current state and table 9, and according to table 10. table 9: truth table ? current state bank n - command to bank n notes: 1?6; notes appear below and on next page current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continue previous operation) lhhh no operation (nop/continue previous operation) idle l l h h active (select and activate row) lllh auto refresh 7 llll load mode register 7 row active lhlh read (select column and start read burst) 10 lhl l write (select column and start write burst) 10 llhl precharge (deactivate row in bank or banks) 8 read (auto precharge disabled) lhlh read (select column and start new read burst) 10 lhl l write (select column and start write burst) 10, 12 llhl precharge (truncate read burst, start precharge) 8 lhhl burst terminate 9 write (auto precharge disabled) lhlh read (select column and start read burst) 10, 11 lhl l write (select column and start new write burst) 10 llhl precharge (truncate writ e burst, start precharge) 8, 11 idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiate d, with auto precharge disabled, and has not yet term inated or been terminated. write: a write burst has been initia ted, with auto precharge disabled, and has not yet term inated or been terminated. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto- precharge enabled: starts with registration of a read command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto- precharge enabled: starts with registration of a write command with auto precharge enabled and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 44 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram truth tables 5. the following states must not be interrupt ed by any executable command; deselect or nop commands must be applied on each pos itive clock edge during these states. 6. all states and se q uences not shown are illegal or reserved. 7. not bank-specific; re q uires that all banks are idle, and bursts are not in progress. 8. may or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/actio n column include reads or writes with auto precharge enabled and reads or writ es with auto pr echarge disabled. 11. re q uires appropriate dm masking. 12. a write command may be applied after the completion of the read burst; otherwise, a burst terminate must be used to end th e read burst prior to asserting a write command. refreshing: starts with registration of an auto refresh command and ends when t rfc is met. once t rfc is met, the ddr sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the mobile ddr sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when t rp is met. once t rp is met, all banks will be in the idle state.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 45 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram truth tables notes: 1. this table applies when cke n -1 was high and cke n is high and after t xsr has been met (if the previous state was self refresh) or after t xp has been met (if the previous state was power-down). 2. this table describes alternate bank operation, except where no ted (i.e., the current state is for bank n and the commands shown are those al lowed to be issued to bank m , assuming that bank m is in such a state that given command is allowable). exceptions are covered in the notes below. 3. current state definitions: read with auto precharge enab led: see following text ? 3a write with auto precharge enab led: see following text ? 3a 3a. the read with auto prec harge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge peri od is defined as if the same burst was exe- cuted with auto precharge di sabled and then followed wi th the earlies t possible pre- charge command that still accesses all of th e data in the burst. for write with auto table 10: truth table ? current state bank n - command to bank m notes: 1?6; notes appear below and on next page current state cs# ras# cas# we# command/action notes any h x x x deselect (nop/continu e previous operation) lhhh no operation (nop/conti nue previous operation) idle x x x x any command allowed to bank m row activating, active, or precharging llhh active (select and activate row) lhlh read (select column and start read burst) 7 lhl l write (select column and start write burst) 7 llhl precharge read (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start new read burst) 7 lhl l write (select column and start write burst) 7, 9 llhl precharge write (auto precharge disabled) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 8 lhl l write (select column an d start new write burst) 7 llhl precharge read (with auto precharge) llhh active (select and activate row) lhlh read (select column and start new read burst) 7, 3a lhl l write (select column and start write burst) 7, 9, 3a llhl precharge write (with auto precharge) llhh active (select and activate row) lhlh read (select column and start read burst) 7, 3a lhl l write (select column an d start new write burst) 7, 3a llhl precharge idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiate d, with auto precharge disabled, and has not yet term inated or been terminated. write: a write burst has been initia ted, with auto precharge disabled, and has not yet term inated or been terminated.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 46 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram truth tables precharge, the precharge period begins when t wr ends, with t wr measured as if auto pre- charge was disabled. the access period starts with registration of the command and ends where the precharge period (or t rp) begins. this device supports concurre nt auto precharge such that when a read with auto precharge enabled or a write with auto prec harge is enabled any command to other banks is allowed, long as that comm and does not interrupt the read or write data transfer already in process. either case, all ot her related limitations apply (e .g., contention between read data and write data must be avoided). 3b. the minimum delay from a read or write command with auto precharge enabled, to a command to a diff erent bank is summarized below. cl ru = cas latency (cl) rounde d up to the next integer bl = bust length 4. auto refresh and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and se q uences not shown are illegal or reserved. 7. reads or writes listed in the command/actio n column include reads or writes with auto precharge enabled and reads or writ es with auto pr echarge disabled. 8. re q uires appropriate dm masking. 9. a write command may be appl ied after the completion of the read burst; otherwise, a burst terminate must be used to end the read burst prior to asserting a write command. from command to command minimum delay (with concurrent auto precharge) write w/ap read or read w/ap write or write w/ap precharge active [1 + (bl/2)] t ck + t wtr (bl/2) t ck 1 t ck 1 t ck read w/ap read or read w/ap write or write w/ap precharge active (bl/2) t ck [cl ru + (bl/2)] t ck 1 t ck 1 t ck
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 47 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram electrical specifications electrical specifications stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. notes: 1. v dd , v dd q, and v dd l must be within 300mv of each other at all times. 2. voltage on any i/o may not exceed voltage on v dd q. table 11: absolute maximum dc ratings parameter symbol min max units notes vdd supply voltage relative to v ss v dd ?1.0 2.3 v 1 vddq supply voltage relative to v ss q v dd q?0.5 2.3 v 1 voltage on any ball relative to v ss v in , v out ?0.5 2.3 v 2 table 12: ac/dc electrical characteristics and operating conditions notes: 1?5; notes appear on pages 52?54; v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v parameter/condition symbol min max units notes supply voltage v dd 1.7 1.9 v 31 i/o supply voltage v dd q 1.7 1.9 v 31 address and command inputs input voltage high v ih 0.8 v dd q v dd q + 0.3 v 25, 32 input voltage low v il ?0.3 0.2 v dd qv 25, 32 clock inputs (ck, ck#) dc input voltage v in ?0.3 v dd q + 0.3 v27 dc input differ ential voltage v id ( dc )0.4 v dd qv dd q + 0.3 v8, 27 ac input differ ential voltage v id ( ac )0.6 v dd qv dd q + 0.3 v8, 27 ac differential crossing voltage v ix 0.4 v dd q 0.6 v dd q v 9, 27 data inputs dc input high voltage v ih ( dc )0.7 v dd qv dd q + 0.3 v 25, 28, 32 ac input high voltage v ih ( ac )0.8 v dd qv dd q + 0.3 v 25, 28, 32 dc input low voltage v il ( dc ) ?0.3 0.3 v dd q v 25, 28, 32 ac input low voltage v il ( ac ) ?0.3 0.2 v dd q v 25, 28, 32 data outputs dc output high voltage: logic 1 (i oh = -0.1ma) v oh 0.9 v dd q? v dc output low voltage: logic 0 (i ol = 0.1ma) v ol ? 0.1 v dd qv leakage current input leakage current any input 0v v in v dd (all other balls not under test = 0v) ii ?1 1 a output leakage current (dqs are disabled; 0v v out v dd q) ioz ?5 5 a
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 48 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram electrical specifications table 13: capacitance notes: 13; notes appear on pages 52?54 parameter symbol min max units notes delta input/output capa citance: dqs, dqs, dm cdio ?1.00pf 21 delta input capacitance: command and address cdi ?1.75pf 26 delta input capacitance: ck, ck# cdck ?0.25pf 26 input/output capacitance: dqs, dqs, dm cio 3.0 5.5 pf input capacitance: address ci 1.5 4.0 pf input capacitance: command ci 1.5 5.0 pf input capacitance: ck, ck# cck 1.5 4.5 pf table 14: i dd specifications and conditions notes: 1?5, 7, 10, 12, 14 no tes appear on pages 52?54; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v parameter/condition symbol max units notes -75 -10 operating one bank active precharge current: t rc = t rc (min); t ck = t ck (min); cke is high; cs is high between valid commands; address inputs are switching every two clock cycles; data bus inputs are stable i dd 08075 ma 19 precharge power-down standby current: all banks idle; cke is low; cs is high; t ck = t ck (min); address and control inputs are switching every two clock cycles; da ta bus inputs are stable i dd 2p 200 200 a 20, 28 precharge power-down standby current with clock stopped: all banks idle; cke is low; cs is high; ck = low, ck# = high; address and control inputs are switching every two clock cycles; data bus inputs are stable i dd 2ps 200 200 a 20, 28 precharge non power-down standby current: all banks idle; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching every two clock cy cles; data bus inputs are stable i dd 2n 25 25 ma 34 precharge non power-down standby current: clock stopped; all banks idle; cke = high; cs = high; ck = low; ck# = high address and control inputs are switching every two clock cycles; data bus inputs are stable i dd 2ns 15 15 ma 34 active power-down standby current: one bank active; cke = low; cs = high; t ck = t ck (min); address and control inputs are switching every two clock cycles; da ta bus inputs are stable i dd 3p 3 3 ma 20, 28 active power-down standby current: clock stopped; one bank active; cke = low; cs = high; ck = low; ck# = high; address and control inputs are switching every two clock cycles; data bus inputs are stable i dd 3ps 3 3 ma 20, 28 active non power-down standby: one bank active; cke = high; cs = high; t ck = t ck (min); address and control inputs are switching every two cycles; data bus inputs are stable i dd 3n 25 25 ma 19 active non-power-down standby: clock stopped; one bank active; cke = high; cs = high; ck = low; ck# = high; address and control inputs are switching every two clock cycles; data bus inputs are stable i dd 3ns 20 20 ma 19 operating burst read: one bank active; bl = 4; t ck = t ck (min); continuous read bursts; i out = 0ma; address inputs are switching; 50% data changing each burst i dd 4r 95 90 ma 19 operating burst write: one bank active; bl = 4; t ck = t ck (min); continuous write bursts; address inputs are switching; 50 percent data changing each burst i dd 4w 95 90 ma 19
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 49 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram electrical specifications figure 30: typical self-refresh current vs. temperature auto refresh: burst refresh; cke = high; address and control inputs are switching; data bus inputs are stable t rc = t rc (min) i dd 5 105 100 ma 35 precharge power-down standby current: all banks idle, cke is low; cs is high; t ck = t ck (min); address and data bus inputs are stable t rc = 15.625s i dd 5a 5 5 ma 24, 35 self refresh: cke = low; t ck = t ck (min); address and control inputs are stable; data bus inputs are stable full array, 85c i dd 6a 300 a 11, 36 full array, 70c i dd 6b 220 a 11, 36 full array, 45c i dd 6c 180 a 11, 36 full array 15c i dd 6d 160 a 11, 36 half array, 85c i dd 6a 220 a 11, 36 half array, 70c i dd 6b 180 a 11, 36 half array, 45c i dd 6c 160 a 11, 36 half array, 15c i dd 6d 150 a 11, 36 1/4 array, 85c i dd 6a 180 a 11, 36 1/4 array, 70c i dd 6b 160 a 11, 36 1/4 array, 45c i dd 6c 150 a 11, 36 1/4 array, 15c i dd 6d 145 a 11, 36 table 14: i dd specifications and co nditions (continued) notes: 1?5, 7, 10, 12, 14 no tes appear on pages 52?54; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v parameter/condition symbol max units notes -75 -10 0.00 50.00 100.00 150.00 200.00 250.00 -40 -30 -20 -10 0 10 20 30 40 50 6 0708090 temperature (c) current (ua) full array half array quarter array
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 50 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram electrical specifications table 15: electrical characteristics and recommended ac operating conditions notes: 1?6, 27; notes appear on pages 52?54; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics symbol -75 -10 units notes parameter min max min max access window of dqs from ck/ck# cl = 3 t ac(3) 2.5 6.0 2.0 7.0 ns 7 cl = 2 t ac(2) 2.0 6.5 2.0 7.0 clock cycle time cl = 3 t ck(3) 7.5 ? 9.6 ? ns 7 cl = 2 t ck(2) 12 ? 15 ? ck high-level width t ch 0.45 0.55 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 0.45 0.55 t ck minimum t cke high/low time t cke 2 ? 2 ? t ck auto precharge write re covery + precharge time t dal ???? 38 dq and dm input hold time relative to dqs t dh 0.75 ? 1.1 ? ns 23, 28, 37 dq and dm input setup time relative to dqs t ds 0.75 ? 1.1 ? ns 23, 28, 37 dq and dm input pulse width (for each input) t dipw t ds + t dh t ds + t dh ns 39 access window of dqs from ck/ck# t dqsck 2.5 6.0 2.5 7.0 ns dqs input high-pulse width t dqsh 0.4 0.6 0.4 0.6 t ck dqs input low-pulse width t dqsl 0.4 0.6 0.4 0.6 t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ? 0.6 ? 0.7 ns 22, 23 write command to first dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs falling edge from ck rising ? hold time t dsh 0.2 ? 0.2 ? t ck dqs falling edge to ck rising ? setup time t dss 0.2 ? 0.2 ? t ck data valid output window (dvw) na t qh - t dqsq t qh - t dqsq ns 22 half-clock period t hp t ch, t cl ? t ch, t cl ? ns 29 data-out high-z window from ck/ck# cl = 3 t hz(3) ? 6.0 ? 7.0 ns 15, 33 cl = 2 t hz(2) ? 6.5 ? 7.0 ns data-out low-z window from ck/ck# t lz 1.0 ? 1.0 ? ns 15 address and control input hold time (fast slew rate) t ih f 1.3 ? 1.5 ? ns 14, 37 address and control input hold time (slow slew rate) t ih s 1.5 ? 1.7 ? ns 14, 37 address and control input setup time (fast slew rate) t is f 1.3 ? 1.5 ? ns 14, 37 address and control input setup time (slow slew rate) t is s 1.5 ? 1.7 ? ns 14, 37 address and control input pulse width t ipw 3.0 ? 3.4 ? ns 39 load mode register command cycle time t mrd 2 ? 2 ? t ck dq?dqs hold, dqs to firs t dq to go non-valid, per access t qh t hp - t qhs ? t hp - t qhs ? ns 22, 23 data hold skew factor t qhs ? 0.75 ? 1 ns active-to-precharge command t ras 4570,0005070,000ns 30 active-to-active/aut o refresh command period t rc 75 ? 80 ? ns active-to-read or write delay t rcd 22.5 ? 30 ? ns average periodic refresh interval t refi ? 15.6 ? 15.6 s 20 auto refresh command period t rfc 97.5 ? 80 ? ns 35 precharge command period t rp 22.5 ? 30 ? ns
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 51 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram electrical specifications dqs read preamble cl = 3 t rpre(3) 0.9 1.1 0.9 1.1 t ck 33 cl = 2 t rpre(2) 0.5 1.1 0.5 1.1 t ck 33 dqs read postamble t rpst 0.4 0.6 0.4 0.6 t ck active bank a to active bank b command t rrd 15 ? 15 ? ns dqs write preamble t wpre 0.25 ? 0.25 ? t ck dqs write preamble setup time t wpres 0 ? 0 ? ns 17, 18 dqs write postamble t wpst 0.4 0.6 0.4 0.6 t ck 16 write recovery time t wr 15 ? 15 ? ns internal write to read command delay t wtr 1 ? 1 ? t ck exit power-down mode to first valid command t xp 8.8 ? 25 ? ns 41 exit self refresh to first valid command t xsr 120 ? 120 ? ns 40 table 15: electrical characteristics and recomm ended ac operating conditions (continued) notes: 1?6, 27; notes appear on pages 52?54; v dd q = +1.8v 0.1v, v dd = +1.8v 0.1v ac characteristics symbol -75 -10 units notes parameter min max min max
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 52 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram notes notes 1. all voltages referenced to vss. 2. all parameters assume proper device initialization. 3. tests for ac timing, i dd , and electrical ac and dc ch aracteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 4. outputs measured with equivalent load: 5. timing and i dd tests may use a v il -to-v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v dd q/2 (or to the crossing point for ck/ck#). the output timing refere nce voltage level is v dd q/2. 6. all ac timings assume an input slew rate of 1v/ns. 7. cas latency definition: for cl = 2, the first data element is valid at ( t ck + t ac) after the clock at which the read command was registered; for cl = 3, the first data element is valid at (2 t ck + t ac) after the first clock at which the read command was registered. 8. v id is the magnitude of the difference between the input level on ck and the input level on ck#. 9. the value of v ix is expected to equal v dd q/2 of the transmitting device and must track variations in the dc level of the same. 10. i dd is dependent on cycle rate, and may be affected by output loading if v dd and v dd q are supplied from the same source. specified values are obtained with mini- mum cycle time for cl = 3 with the outputs open. 11. enables on-chip refresh and address counters. 12. i dd specifications are tested after the device is properly. 13. this parameter is sampled. v dd = +1.8v 0.1v, v dd q = +1.8v 0.1v, f = 100 mhz, t a =25oc, v out ( dc ) = v dd q/2, v out (peak-to-peak) = 0.2v. dm input is grouped with i/o balls, reflecting the fact th at they are matched in loading. 14. fast command/addres s input slew rate 1v/ns. slow command/address input slew rate 0.5v/ns. if the slew rate is less than 0.5v/ns, timing must be derated: t is has an additional 50ps per each 100mv/ns reduct ion in slew rate from the 0.5v/ns. t ih remains constant. 15. t hz and t lz transitions occur in the same access time windows as valid data transi- tions. these parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (hz) or begins driving (lz). i/o 20 pf i/o 10 pf full-drive strength half-drive strength 50 50 i/o 5 pf quarter-drive strength 50
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 53 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram notes 16. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, bu t system performance (bus turnaround) will degrade accordingly. 17. this is not a device limit. the device will operate with a negative value, but system performance could be degraded due to bus turnaround. 18. it is recommended that dqs be valid (high or low) on or before the write command. 19. min ( t rc or t rfc) for i dd measurements is the smallest multiple of t ck that meets the minimum absolute value for the respective parameter. t ras (max) for i dd measure- ments is the largest multiple of t ck that meets the maximum absolute value for t ras. 20. the refresh period equals 64ms. this eq uates to an average refresh rate of 15.625s. 21. the i/o capacitance per dqs and dq byte/group will not differ by more than this maximum amount for any given device. 22. the valid data window is derived by achieving other specifications: t hp ( t ck/2), t dqsq, and t qh ( t hp - t qhs). the data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. the clock is allowed a maximum duty cycle variation of 45/55. functionality is uncertain when operating beyond a 45/55 ratio. 23. referenced to each output group: ldqs with dq0?dq7; and udqs with dq8?dq15. 24. this limit is a nominal value and does not result in a fail. cke is high during refresh command period ( t rfc [min]) else cke is low (i.e., during standby). 25. to maintain a valid level, the transitioning edge of the input must: a. sustain a constant slew rate from the current ac level through to the target ac level, v il ( ac ), or v ih ( ac ). b. reach at least the target ac level. c. after the ac target level is reached, co ntinue to maintain at least the target dc level, v il ( dc ) or v ih ( dc ). 26. the input capacitance per ball group will not differ by more than this maximum amount for any given device. 27. ck and ck# input slew rate must be 1v/ns (2v/ns if measured differentially). 28. dq and dm input slew rates must not deviate from dqs by more than 10 percent. if the dq/dm/dqs slew rate is less than 0.5v/ns, timing must be derated: 50ps must be added to t ds and t dh for each 100mv/ns reduction in slew rate. if slew rate exceeds 4v/ns, functionality is uncertain. 29. t hp (min) is the lesser of t cl minimum and t ch minimum actually applied to the device ck and ck# inputs, collectively. 30. reads and writes with auto precharge are not allowed to be issued until t ras (min) can be satisfied prior to the intern al precharge command being issued. 31. any positive glitch must be less than 1/ 3 of the clock cycle and not more than +200mv or 2.0v, whichever is less. any negative glitch must be less than 1/3 of the clock cycle and not exceed either -150mv or 1.6v, whichever is more positive. 32. v ih overshoot: v ih (max) = v dd q + 0.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = -0.5v for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 33. t hz (max) will prevail over t dqsck (max) + t rpst (max) condition. 34. i dd 2n specifies dq, dqs, and dm to be driven to a valid high or low logic level. 35. cke must be active (high) during the entire time a refresh command is executed. that is, from the time the auto refres h command is registered, cke must be active at each risi ng clock edge, until t rfc later.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 54 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram notes 36. values for i dd 6 85c are guaranteed for the entire temperature range. all other i dd 6 values are estimated. 37. the transition time for in put signals (cas#, cke, cs#, dm, dq, dqs, ras#, we#, and addresses) are me asured between v il ( dc ) to v ih ( ac ) for rising input signals and v ih ( dc ) to v il ( ac ) for falling input signals. 38. t dal = ( t wr/ t ck) + ( t rp/ t ck): for each term, if not already an integer, round to the next higher integer. 39. these parameters guarantee device timing but they are no t necessarily tested on each device. 40. clock must be toggled a minimum of two times during this period. 41. clock must be toggled a minimum of one time during this period.
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 55 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams timing diagrams figure 31: x16 data output timing ? t dqsq, t qh, and data valid window notes: 1. dq transitioning af ter dqs transition define t dqsq window. ldqs defines the lower byte and udqs defines the upper byte. 2. dq0, dq1, dq2, dq3, dq4, dq5, dq 6, or dq7. 3. t dqsq is derived at each dqs clock edge and is not cumulative over time and begins with dqs transition and ends with the last valid dq transition. 4. t qh is derived from t hp: t qh = t hp - t qhs. 5. t hp is the lesser of t cl or t ch clock transition collectively when a bank is active. 6. the data valid window is derive d for each dqs transition and is t qh minus t dqsq. 7. dq8, dq9, dq10, dq11, dq 12, dq13, dq14, or dq15. dq (last data valid) 2 dq 2 dq 2 dq 2 dq 2 dq 2 dq 2 ldqs 1 dq (last data valid) 2 dq (first data no longer valid) 2 dq (first data no longer valid) 2 dq0 - dq7 and ldqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n ck ck# t1 t2 t3 t4 t2n t3n t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 data valid window data valid window dq (last data valid) 7 dq 7 dq 7 dq 7 dq 7 dq 7 dq 7 udqs 1 dq (last data valid) 7 dq (first data no longer valid) 7 dq (first data no longer valid) 7 dq8 - dq15 and udqs, collectively 6 t2 t2 t2 t2n t2n t2n t3 t3 t3 t3n t3n t3n t qh 4 t qh 4 t qh 4 t qh 4 t dqsq 3 t dqsq 3 t dqsq 3 t dqsq 3 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t hp 5 t qh 4 t qh 4 data valid window data valid window data valid window data valid window data valid window upper byte lower byte data valid window
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 56 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 32: data output timing ? t ac and t dqsck notes: 1. dq transitioning af ter dqs transition define t dqsq window. 2. all dq must transition by t dqsq after dqs transiti ons, regardless of t ac. 3. t ac is the dq output window relative to ck, and is the ? long term ? component of dq skew. figure 33: data input timing notes: 1. t dsh (min) generally occurs during t dqss (min). 2. t dss (min) generally occurs during t dqss (max). 3. write command issued at t0. 4. ldqs controls the lower byte and udqs controls the upper byte. 5. ldm controls the lower byte an d udm controls the upper byte. ck ck# dqs, or ldqs/udqs 1 all dq values, collectively 2 t0 t1 t2 t3 t4 t5 t2n t3n t4n t5n t6 t rpre t hz (max) command nop nop nop nop t dqsck (max) nop t ac (max) cl = 3 nop read t2 t dqsck (max) t rpst t2n t3 t3n t4n t5 t5n t4 t dq ss t dq s h t wp s t t dh t d s t dq s l t d ss 2 t d s h 1 t d s h 1 t d ss 2 c k c k# t0 3 t1 t1n t2 t2n t3 di b don ? t c are tran s itionin g data t wpre t wpre s dq s 4 dq dm 5
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 57 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 34: initialize and load mode registers notes: 1. pre = precharge command, lmr = load mode register command, ar = auto refresh command, act = active co mmand, ra = row address, ba = bank address. 2. nop or deselect commands are re q uired for at least 200s. 3. other valid commands are possible. 4. nops or deselects are re q uired during this time. cke lvcmos high level dq bank address (ba0, ba1) load standard mode register load extended mode register t mrd 4 t mrd 4 t rfc 4 t rfc 4 power-up: v dd and ck stable t = 200s high-z dm dqs high-z addresses ra a10 ra ck ck# t ch t cl t ck v dd v dd q command 1 lmr nop lmr ar t is t ih ba0 = l, ba1 = l t is t ih ba0 = l, ba1 = h t is t ih code code t is t ih code code pre all banks t is t ih t0 t1 ta0 tb0 tc0 td0 te0 tf0 don?t care ba ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp 4 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop 2 ar act ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) nop 3 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( )
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 58 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 35: power-down mode (active or precharge) notes: 1. if this command is a precharge (or if the device is already in th e idle state), then the power-down mode shown is precharge power-down . if this command is an active (or if at least one row is already active ), then the power-down mode shown is active power-down. 2. no column accesses are allowed to be in progress at the time power-down is entered. 3. there must be at least one clock pulse during t xp time. c k c k# c ommand v alid 1 nop addr c ke dq dm dq s nop t c ke t c h t c l t i s t i s t ih t i s t i s t ih t ih enter 2 powe r -dow n mo d e exit 3 powe r -dow n mo d e must not ex c ee d refresh d evi c e limits ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t a 0 t a 1 t a 2 t2 nop don ? t c are ( ) ( ) ( ) ( ) v ali d ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t b 1 t xp v ali d v ali d t c k
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 59 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 36: auto refresh mode notes: 1. pre = precharge, act = ac tive, ar = auto refresh, ra = row address, ba = bank address. 2. nop commands are shown for ease of illustra tion; other valid commands may be possible at these times. cke must be active during clock positive transitions. 3. nop or command inhibit are the on ly commands allowed until after t rfc time, cke must be active during cloc k positive transitions. 4. ? don?t care ? if a10 is high at this point; a10 must be high if more than one bank is active (i.e., must precharge all active banks). 5. dm, dq, and dqs signals are all ? don?t care ? /high-z for operations shown. 6. the second auto refresh is not re q uired and is only shown as an example of two back-to- back auto refresh commands. c k c k# c ommand 1 nop 2 valid valid nop 2 nop 2 pre c ke ra a0?a9, a11 a10 1 ba0, ba1 1 bank(s) 4 ba ar nop 2, 3 ar 6 nop 2, 3 a c t nop 2 one bank all bank s c k t c h t c l t i s t i s t ih t ih t i s t ih ra ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ) ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ) ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq 5 dm 5 dq s 5 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rf c 6 t rp t rf c t0 t1 t2 t3 t4 ta0 t b 0 ta1 t b 1 t b 2 don ? t c are ) ) ( ) ( ) 1
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 60 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 37: self refresh mode notes: 1. clock must be stable before exiting self refresh mode. that is, th e clock must be cycling within specifications by ta0. 2. device must be in the all banks idle sta te prior to entering self refresh mode. 3. nops or deselect are re q uired for t xsr time with at least two clock pulses. 4. ar = auto refresh command. c k 1 c k# c ommand 4 nop ar addr c ke 1 valid dq dm dq s valid nop t rp 2 t c h t c l t c k t i s t x s r 3 t i s t ih t i s t i s t ih t ih t i s enter self refresh mode exit self refresh mo d e ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t b 0 ta1 ( ) ( ) ( ) ( ) ( ) ( ) don ? t c are ( ) ( ) ( ) ( ) ta0 (1)
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 61 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 38: bank read ? without auto precharge notes: 1. d out n = data-out from column n . 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ? don?t care ? if a10 is high at t5. 5. ra = row address, ba = bank addr ess, pre = precharge, act = active. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. the precharge command can only be applied at t5 if t ras minimum is met. 8. refer to figure 31 on page 55 and figure 32 on page 56 for detailed dqs and dq timing. ck ck# cke a10 ba0, ba1 t ck t ch t cl t is t ih t is t ih t is t ih t is t ih t is t ih ra t rcd t ras 7 t rc t rp cl = 2 dm t0 t1 t2 t3 t4 t5 t5n t6n t6 t7 t8 dq 1 dqs case 1: t ac (min) and t dqsck (min) 8 case 2: t ac ( max) and t dqsck ( max) 8 dq 1 dqs t hz ( max) nop 6 nop 6 command 5 3 act ra ra col n read 2 bank x ra ra ra bank x act bank x nop 6 nop 6 nop 6 don?t care transitioning data a0?a9 a11 pre 7 bank x 4 t rpre t rpre t ac ( max) all banks one bank d out n d out n + 1 d out n + 2 d out n + 3 d out n d out n + 1 d out n + 2 d out n + 3 t lz (min) t lz (min) t dqsck (min) t ac (min) t rpst t rpst t dqsck (max)
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 62 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 39: bank read ? with auto precharge notes: 1. d out n = data-out from column n . 2. bl = 4 in the case shown. 3. enable auto precharge. 4. pre = precharge, act = active, ra = row address, ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. refer to figure 31 on page 55 and figure 32 on page 56 for detailed dqs and dq timing. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t r c t rp c l = 2 dm t0 t1 t2 t3 t4 t5 t5n t 6 n t 6 t7 t8 dq 1 dq s c ase 1: t a c ( min) an d t dq sc k ( min) 6 c ase 2: t a c ( max) an d t dq sc k ( max) 6 dq 1 dq s t hz ( max) nop 5 nop 6 c ommand 4 3 a c t ra ra c ol n read 2 bank x ra ra ra bank x a c t bank x nop 5 nop 5 nop 5 don ? t c are tran s itionin g data a0?a9 a11 nop 5 t rpre t dq sc k ( max) t a c ( max) d out n d out n + 1 d out n + 2 d out n + 3 d out n d out n + 1 d out n + 2 d out n + 3 t dq sc k ( min) t a c ( min) t rp s t t lz ( min) t rpre t rp s t t lz ( min)
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 63 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 40: bank write ? without auto precharge notes: 1. di b = data-out from column n . 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ? don?t care ? if a10 is high at t5. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t rp t wr t0 t1 t2 t3 t4 t5 t5n t 6 t7 t8 t4n nop 6 nop 6 c ommand 5 3 a c t ra ra c ol n write 2 nop 6 one bank all bank s bank x pre bank x nop 6 nop 6 nop 6 t dq s l t dq s h t wp s t bank x 4 dq 1 dq s dm di b t d s t dh don ? t c are tran s itionin g data t dq ss (nom) t wpre t wpre s a0-a9 a11
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 64 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 41: bank write ? with auto precharge notes: 1. di b = data-out from column n . 2. bl = 4 in the case shown. 3. disable auto precharge. 4. pre = precharge, act = active, ra = row address, ba = bank address. 5. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 6. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 7. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t rp t wr t0 t1 t2 t3 t4 t5 t5n t 6 t7 t8 t4n nop 5 nop 5 c ommand 4 3 a c t ra ra c ol n write 2 nop 5 bank x nop 5 bank x nop 5 nop 5 nop 5 t dq s l t dq s h t wp s t dq 1 dq s dm di b t d s t dh t dq ss (nom) don ? t c are tran s itionin g data t wpre s t wpre a0-a9 a11
pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 65 ?2004 micron technology, inc. all rights reserved. 128mb: 8 meg x 16 mobile ddr sdram timing diagrams figure 42: write ? dm operation notes: 1. di b = data-out from column n . 2. bl = 4 in the case shown. 3. disable auto precharge. 4. ? don?t care ? if a10 is high at t5. 5. pre = precharge, act = active, ra = row address, ba = bank address. 6. nop commands are shown for ease of illustrati on; other commands may be valid at these times. 7. t dsh is applicable during t dqss (min) and is referenced from ck t4 or t5. 8. t dsh is applicable during t dqss (min) and is referenced from ck t5 or t6. c k c k# c ke a10 ba0, ba1 t c k t c h t c l t i s t i s t ih t i s t i s t ih t ih t ih t i s t ih ra t r c d t ra s t rp t wr t0 t1 t2 t3 t4 t5 t5n t 6 t7 t8 t4n nop 6 nop 6 c ommand 5 3 a c t ra ra c ol n write 2 nop 6 one bank all bank s bank x pre bank x nop 6 nop 6 nop 6 t dq s l t dq s h t wp s t bank x 4 dq 1 dq s dm di b t d s t dh don ? t c are tran s itionin g data t dq ss (nom) t wpre s t wpre a0?a9 a11
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo ar e trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits spec ified over the power supply an d temperature range set forth herin. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 128mb: 8 meg x 16 mobile ddr sdram package dimensions pdf: 09005aef8199c1ec/source: 09005aef81a19319 micron technology, inc., reserves the right to change products or specifications without notice. mt46h8m16lf_1.fm - rev. k 7/07 en 66 ?2004 micron technology, inc. all rights reserved. package dimensions figure 43: 60-ball vfbga package notes: 1. dimensions are in millimeters. ball a1 id 1.00 max mold compound: epoxy novolac substrate material: plastic laminate solder ball material: 96.5% sn, 3% ag, 0.5% cu (lead-free) solder ball pads: ? 0.40 solder mask defined ball a9 ball a1 8.00 0.10 4.00 0.05 3.20 ball a1 id 60x ? 0.45 solder ball diameter refers to post reflow condition. the pre- reflow diameter is ? 0.42 c l c l 0.80 typ 5.00 0.05 3.60 7.20 10.00 0.10 0.65 0.05 0.10 c c seating plane 6.40 0.80 typ

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